The present invention relates to a logic system which may be associated with a memory device containing defects and sufficient additional storage so that the memory may retain its nominal size in the presence of such defects. More particularly, this invention relates to a logic system for use with bubble memories designed in the major loop-minor loop field access arrangement. Specifically, this invention relates to the provision of a Programmable Read Only Memory (PROM) containing a defect map related to the associated memory device, a shift register which may be selectively inserted in the data stream, a position counter associated with a multiplexer to control the output of the shift register through which data passes and logic means to control the device.
Numerous different attempts are found in the prior art to create a certain measure of fault tolerance in memory devices. Many such efforts rely on changes in structure in the memory device so that defective areas may be bypassed. For example, in the bubble memory art there are several patents showing magnetic bubble structures having alterable bubble paths to allow for fault tolerance. Similarly, there are many devices in the memory art showing methods whereby data is stored in a secondary memory and logic is used to selectively replace defective areas of the major or primary memory with the limited storage capacity of the secondary memory. Thus, those logic schemes substitute good memory for bad memory in various ways.
Techniques of adjusting the structure of a bubble memory chip to allow for faults requires significant modification of the basic structure and increased complexity. Furthermore, such chips are in some cases extremely vulnerable to a single defect in certain areas of the memory relating to the logic structure for adjustment in the presence of defects. Thus, although such a memory would tolerate a fault in the memory portion, a fault in the logic portion of the memory would still cause failure. Systems relying on an external memory or secondary memory, combined with logic to make a primary memory usable, are more complex in that there are additional memory devices which must be connected and associated with the primary device.
The present invention relates to a logic system which may be used with a defect map independently of whether or not the defect map is located on the bubble memory chip or whether it is externally located. This invention may be used with a secondary memory flaw map on a single chip with the main bubble memory such as is shown in copending patent application, Ser. No. 841,505.
U.S. Pat. No. 3,792,450 shows a bubble memory chip containing flaw information together with external logic which uses the flaw storage on the bubble chip to implement the fault tolerant design. It has been noted that the invention shown in the subject patent does not have the capability of mapping out or rejecting minor loops in the bubble memory at will. Minor loops are rejected or ignored only if they fail to propagate a bubble around completely. The invention described in this application has the flexibility of mapping out spare or redundant minor loops that are not necessarily defective. It has also been noted that if the control loop shown in the subject patent contains a defect, the bubble memory chip will have to be discarded for the presence of a single error in such locations. With respect to the logic design shown in the subject patent, an entire block of data being written into or read from the storage must be externally buffered in order to maintain a constant stream of read-write data for the memory. A buffer of sufficient size to handle all data is an unnecessary burden. The present application uses a shift register to create the necessary buffering but the invention herein described has the advantage that only as much buffering is required as corresponds to the maximum acceptable number of defective minor loops. Thus, it is not necessary in the present invention to provide buffering capacity equivalent to all good memory minor loops.